Interconnecting substrates for microelectronic dies, methods for forming vias in such substrates, and methods for packaging microelectronic devices
Interconnecting substrates for microelectronic dies, methods for forming vias in such substrates, and methods for packaging microelectronic devices
Patent Agent: Perkins Coie LLP Patent-sea - Seattle, WA, US
Patent Inventors: Chin Hui Chong, Choon Kuan Lee, David J. Corisis
Applicaton #: 20070045834
Class: 257734000 (USPTO)
Related Patents: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Combined With Electrical Contact Or Lead
03/01/07
Substrates for mounting microelectronic dies, methods for forming vias in such substrates, and methods for packaging microelectronic devices are disclosed herein. A method of manufacturing a substrate in accordance with one embodiment of the invention includes forming a conductive trace on a first side of a sheet of non-conductive material, and forming a via through the non-conductive material from a second side of the sheet to the conductive trace. The method further includes removing a section of the non-conductive material to form an edge of the non-conductive material extending across at least a portion of the via. In one embodiment, forming the edge across the via exposes at least a portion of the second conductive trace for subsequent attachment to a terminal on a microelectronic die.
TECHNICAL FIELD
[0001] The following disclosure relates generally to interconnecting substrates for microelectronic dies and, more particularly, to methods for coupling microelectronic dies to interconnecting substrates having conductive traces on two sides.
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